1. Field of the Invention
The present invention is directed to the design and manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to methods of avoiding substrate noise in integrated circuits.
2. Description of the Prior Art
A typical design for an integrated circuit die includes N-type devices formed in N-type wells (N-wells) in a P-type substrate (P-substrate). The N-type devices are organized into APR (automatic placement and routing) blocks to perform a specific set of functions. Multiple N-type devices that are formed in the same P-substrate may receive and transmit switching noise through N-well openings through a surface boundary and through a side boundary of the P-substrate to adjacent N-type devices. The switching noise in the P-substrate is referred to as substrate noise. In a conventional design flow, the spacing between APR blocks is manually increased to reduce the substrate noise, which increases the parasitic resistance of the P-substrate and attenuates the substrate noise level between the N-type devices.